1. Field of the Invention
The present invention relates to a memory device, and in particular to a memory device which has an internal power generator for stably supplying power to an internal circuit.
2. Related Arts
Recent semiconductor memory devices, particularly dynamic random access memories (DRAMs), employ voltages, higher than the power source voltage which is externally supplied, either for a gate voltage of a cell transistor or for a back bias voltage so that a write operation and read operation become faster. Thus, a pump circuit is provided inside a DRAM to generate an internal power source voltage which is higher than the externally supplied power source voltage.
Specifically, two types of pump circuit are provided: a main pump circuit and a sub-pump circuit. The main pump circuit is operated when power is on and when a cell transistor is switched, while the sub-pump circuit is operated to compensate for the electric charge leakage which occurs when the cell transistor is not driven. That is, at deactivation time when no writing or reading is performed and only current leakage need be compensated for, only the sub-pump circuit, which has a low charge supply capability and consumes only a small amount of power, is operated in order to reduce the power consumed by the DRAM.
As the memory capacity is increased, in the DRAM a plurality of banks are employed. For the bank arrangement, a memory cell array is divided into a plurality of banks, with each bank then being divided into a plurality of blocks. The individual banks are activated independently, and when a bank is no longer required to operate, it is deactivated in order to reduce the consumption of power. In addition, in order to supply the current to the memory cell arrays of the individual blocks with a low impedance, a main pump circuit and a sub-pump circuit are provided for each block.
At present, there is a drastically increased demand for memory devices, particularly for DRAM, with which high writing and reading speeds and high integration are possible. However, when the speed of DRAM is increased, the power consumed by one of the cell transistors increases, so that a pump circuit having a high charge supply capability is required. As a result, the size of the area required for the pump circuit is increased, and the power consumed by the pump circuit is also increased.
In a case where a main pump circuit and a sub-pump circuit are provided for each block, but only the sub-pump circuit is operated for the block at the deactivation time, the power consumption is reduced. However, the ratio of the total area for the main pump circuits and the sub-pump circuits to the area of the memory cell array is increased, and the demand of high integration of the DRAM is not met.